1. Field of the Invention
The present invention relates to a communication control apparatus and a control method.
2. Description of the Related Art
During recent years, a variety of devices have been directly connected to wire/wireless networks. As examples of such devices, there are a mobile terminal, a printer, a camera, a copying machine, a display, a video apparatus, an acoustic apparatus and others. The processing ability of the main CPUs installed on these devices is often lower than that of CPUs installed on personal computers. The following two methods are considered when Internet standard protocols such as TCP/UDP/IP normally used in networks attempt to realize using resources of such devices.
The first method is to execute TCP/IP protocol stacks with a main CPU. In this situation, the main CPU has to execute at least the communication process and the application process. If a communication process and an application process are performed in parallel, the processing speed of either one process or both processes is possibly decreased The second method is to give the main CPU independence from the communication process. More specifically, there is a method of utilizing an auxiliary device specifically performing a protocol process such as TOE (TCP/IP offload engine) or the method of executing protocol stacks using a sub-CPU which is independent from the main CPU. In this method, the effect on the process ability given by each of the communication process and the application process becomes small because the main CPU is independent from the communication process.
The method regarding TOE has been proposed in Japanese Patent Laid-Open No. 2003-143221 (hereafter, Document 1). Document 1 shows the TCP/IP engine which has an interface with an application CPU executing applications and has an arbitration function of sending by priority the application data input from the application CPU. Further, it shows the method of how to use DMA (Direct Memory Access) in order to transfer the application data between the application CPU and TCP/IP engine.
The data processing method in communication process has been proposed in Japanese Patent Laid-Open No. 2005-137022 (hereafter, Document 2). Document 2 shows the method of processing packets after separating each received packets into a header and data and copying them respectively into different regions. The integrated circuit which can be applied to a communication control apparatus has been proposed in Japanese Patent Laid-Open No. 2006-050503 (hereafter, Document 3). Document 3 shows the method of analyzing received packets, determining the area of memory on which the packets should be copied based on the result of analysis, and transferring the packets to the determined area.
It is common to copy received packets into reception buffers in order to analyze them after the packets including a header and a data portion are received from a network. If the object of the analysis is only a header portion in the received packets, and assuming that the analysis is started after copying all contents including the header portion and the data portion into the reception buffer, wasted latency by starting the analysis will be required. In this way, the throughput of communication may be decreased.
It is possible to perform the analysis before finishing the copy process if the packets are copied into the reception buffer by using the device, for example, DMAC (Direct Memory Access Controller) which is independent from the device having analysis function such as CPU and others. That is, if the CPU performs the analysis of the header portion just after the header portion is finished copying via DMA, the analysis process and the copy process of the data can be performed in parallel even while DMAC copies the packets. However, if all of the header portion and the data portion are copied into the buffer on the same memory, the following problems will occur. That is, the processing efficiency can be decreased because the memory access for the copy of the data portion using DMA and the memory access by CPU for the header analysis compete against each other.